1. Field of the Invention
This invention relates to semiconductor devices and more particularly, to an improved method for fabricating semiconductor devices, such as bipolar or field effect-type integrated circuit transistors, wherein electric characteristics of the interconnections between polycrystalline semiconductors and semiconductive regions with high impurity concentrations formed in a single crystalline semiconductor substrate are significantly improved.
2. Description of the Prior Art
As is known in the art, utility of a polycrystalline semiconductor in semiconductor integrated circuits of the bipolar or electric field type transistor has been recently recognized for achieving well-miniaturized elements of the circuits. For instance, in the field of bipolar technologies for silicon semiconductor, the usual practice is to employ polycrystalline silicon (polysilicon) as a material for fine wiring or as an impurity diffusion source for the formation of shallow junction. In particular, it is essential for high speed operations that a polysilicon lead electrode be used to form an emitter region of fine plane dimensions.
As an example of an emitter fabrication method wherein arsenic is diffused from polycrystalline silicon, there is known a self-aligned double diffusion polysilicon technology (Kikuchi et al, International Electron Device Meeting Technical Digest of Papers, pp. 420-423, 1986). In this method, arsenic which has been implanted into an about 300 namometer thick polysilicon film at a dose of 10.sup.16 /cm.sup.2 is thermally diffused into a single crystalline silicon substrate at 900.degree. C. for 30 minutes. As a result, a shallow emitter having a junction depth of about 50 nanometers is formed. According to our experiments, when arsenic is subjected to heat treatment at relatively high temperatures of 1000.degree. C. for 20 minutes to permit the arsenic to be diffused into the silicon substrate through the polysilicon thin film as set out above, an emitter having a junction depth of about 180 nanometers can be obtained. This is particularly shown in FIG. 1 which shows the relation between the concentration of arsenic and the depth of junction.
On the other hand, where an emitter having a greater depth is to be formed, diffusion under higher temperature and longer time conditions is necessary. This will inevitably entail deep diffusion of a semiconductive region such as a base which has been formed in a preceding step. It is thus known that a transistor structure suitable for high speed operations is difficult to obtain. More particularly, during the relatively high temperature treatment procedure (1000.degree. C., 20 minutes) of forming a high-speed emitter having a depth of 180 nanometers, the depth of the base region formed by ion implantation such as of boron becomes undesirably as great as 400 to 500 nanometers or over. For instance, when a commercially available ion implanter is used to form a p-type base region at a minimum value of steady implantation acceleration energy, say, 25 KeV, which is now the most stable and is substantially free of deviation, the junction depth of the base becomes about 500 nanometers. At the time, when the depth of the emitter is 180 nanometers, the resultant transistor has a width of the base layer of about 320 nanometers. A typical collector cut-off frequency (f.sub..tau.) of the transistor having a base width of 320 nanometers is about 5 GHz. In order to easily make a transistor whose cut-off frequency is 10 GHz, the base width should be from 100 to 200 nanometers. In this case, a necessary depth of the emitter formed by diffusion from the polysilicon is about 300 nanometers, requiring an abnormal heat treatment at very high temperatures for a long time. This leads to formation of an undesirably deep base. Thus, this procedure cannot provide a transistor having a base width of from 100 to 200 nanometers.
On the other hand, for the formation of an emitter/base junction adapted for the fabrication of bipolar transistor, there is known a method wherein an impurity such as As is ion implanted directly into a base of the p-type. For instance, as shown in FIG. 2, when 1.times.10.sup.16 /cm.sup.2 of arsenic is directly ion implanted into silicon at an implantation accelerator energy of 50 KeV and thermally treated at 1000.degree. C. for a diffusion time of 60 minutes (t=60 minutes), the depth of the resultant emitter is about 430 nanometers. When the diffusion time is 20 minutes (T=20 minutes), the depth is about 260 nanometers. When the thermal treatment is not effected, or immediately after the ion implantation (t=0 minute), the depth is about 100 nanometers. As is shown in FIG. 1, the depth of the emitter which is obtained by diffusing arsenic from polycrystalline silicon by thermal treatment at 1000.degree. C. for 20 minutes is about 180 nanometers. On the other hand, the depth of the emitter which is formed by direct ion implantation of arsenic into silicon and subsequent heat treatment under the same conditions of 1000.degree. C. and 20 minutes as used in FIG. 1 is 260 nanometers, which is larger by 80 nanometers than that of the emitter diffused from polysilicon. The amount of the arsenic impurity in the silicon is larger for the emitter formed by the direct ion implantation, resulting favorably in a lower emitter resistance. Moreover, with the emitter formed by the direction ion implantation, it is usual to take a metal electrode directly from the emitter surface without use of any polycrystalline silicon electrode as an intermediate layer. However, as an opening or contact hole of the emitter is made finer, polysilicon which has better coverage over the opening than A1 is now used to prevent disconnection of electrode.
The problem involved in the formation of the emitter by diffusion from polycrystalline silicon set out with reference to FIG. 1 is the influence of a silicon oxide thin film naturally formed between the polycrystalline silicon and single crystal silicon. The natural oxide film on the single crystal silicon grows in a thickness not larger than about 2 nanometers when a non single crystalline thin film such as of polycrystalline silicon, amorphous silicon or the like is deposited. A thicker oxide film results in a smaller diffusion depth of the emitter. Moreover, the series resistance of the emitter increases as the thickness of the oxide film is increased causing transistor characteristics to degrade or deviate significantly.
The problem on the unstability caused by the natural oxide film becomes more serious in the case where a deep emitter is initially formed by ion implantation as shown in FIG. 2, after which a non single crystalline electrode such as of polycrystalline or amorphous silicon is led out from the emitter. More particularly, when a polycrystalline silicon film is deposited on the silicon surface containing an impurity of high concentration such as arsenic, the natural oxide film grows up thicker on the silicon surface than on a silicon surface with an impurity of lower concentration. This will cause the ohmic contact between the emitter and the deposited polycrystalline silicon to become increasingly worsened, resulting in a considerable increase of the emitter resistance.
Another problem involved in prior art methods is that the formation of an emitter having a depth of, for example, about 300 nanometers requires a long-term thermal treatment of 1000.degree. C. and for about 60 minutes as shown in FIG. 1. Such a long-term thermal treatment causes a base region formed during the same thermal treatment to be diffused more deeply. The resultant transistor is not adapted for high speed purposes.